1. Field of the Invention
The present invention relates to the structure of electrode contact portions of a semiconductor integrated circuit and, more particularly, to the structure of electrode contact portions of thin-film transistors (TFTs) used in an active matrix liquid crystal display. The invention also relates to process steps for fabricating TFTs having such a structure.
2. Description of the Related Art
Active matrix liquid crystal displays have been known. Such a liquid crystal display comprises a substrate made of glass or quartz. TFTs are formed and disposed at pixels on the substrate. Pixel portions of the general active matrix liquid crystal display are manufactured by the fabrication steps described below.
FIGS. 6A and 6B are top views of one pixel portion of this conventional active matrix liquid crystal display, illustrating its process sequence. FIG. 8A is a cross-sectional view taken on line A-A' of FIG. 6A. FIG. 8B is a cross-sectional view taken on line B-B' of FIG. 6B. FIG. 9A is a cross-sectional view taken on line a-a' of FIG. 7.
First, as shown in FIGS. 6A and 8A, a silicon oxide film 12 is formed as a buffer layer on a glass substrate 11. Then, an amorphous silicon film that will act as a starting film for the active layer of TFTs is formed. Thereafter, the amorphous silicon film is irradiated with laser light or heat-treated to convert the amorphous silicon film into a crystalline silicon film.
The resultant crystalline silicon film is then patterned to form an active layer pattern 13. FIG. 6A is a top view of this active layer pattern 13. FIG. 8A is a cross-sectional view taken on line A-A' of FIG. 6A.
A metallization layer is grown to form a gate electrode. This metallization layer can be fabricated from various silicide materials or metallic materials. The metallization layer is patterned to form a gate electrode 14. As shown in FIG. 6B, the gate electrode 14 is formed so as to extend from a gate line 15. This gate line 15, other gate lines (not shown), and source lines (formed later) are arranged in rows and columns in an active matrix region.
Then, using the gate electrode 14 as a mask, dopant ions are introduced, and a source region 16 and a drain region 18 are formed by self-aligned techniques. If an N-channel TFT should be fabricated, P (phosphorus) is implanted. If a P-channel TFT should be manufactured, B (boron) is lodged. During this implantation of the dopant ions, a channel region 17 is defined in a self-aligned manner. As a result, a state represented by the cross-sectional view of FIG. 8B is obtained. FIG. 8B is taken on line B-B' of FIG. 6B. Subsequently, a silicon nitride film or silicon oxide film is formed as an interlayer dielectric film 19. The resultant state is shown in FIG. 8C.
As shown in FIG. 8D, contact holes 20 and 21 are formed in the interlayer dielectric film 19 to make contact with the source region 16 and the drain region 18, respectively. Then, as shown in FIG. 9A, electrodes 22 and 23 in contact with the source region 16 and the drain region 18, respectively, are formed at the same time. FIG. 7 is a top view of the structure shown in the cross-sectional view of FIG. 9A, which is taken along line a-a' of FIG. 7.
As shown in FIG. 7, the contact to the source line 22 is larger in area than the source region 16 in the active layer. Also, the electrode pattern 23 for making contact with the drain region 18 is considerably larger than the pattern of the drain region 18. This is due to a margin set to cope with misalignment of masks caused during formation of the contact holes 20 and 21 and misalignment of the conductive lines 22, 23 with the electrode pattern caused during formation of them.
These kinds of misalignments are produced to a considerable level by shrinkage of the glass substrate and by the misalignment introduced by the exposure machine itself. Generally, where a liquid crystal display is manufactured, a substrate made of glass is used. Also, the substrate has a large area. Therefore, misalignment of the order of micrometers takes place. Consequently, the margin must be set, taking account of the above-described misalignments.
After obtaining the state shown in FIG. 9A, a resinous film 25 is formed as a second interlayer dielectric film 25. The use of the resinous material can flatten the surface. In this way, a state shown in FIG. 9B is obtained.
Then, contact holes reaching the electrodes 23 are formed. Pixel electrodes 26 of ITO are formed, thus resulting in a state shown in FIG. 9C. A process sequence for fabricating TFTs used to construct a peripheral drive circuit or other integrated circuit is schematically shown in the top views of FIGS. 12A, 12B, and 13.
In the state shown in FIG. 12A, a gate insulator film (not shown) is formed on an active layer 1201 consisting of a silicon film. A gate electrode 1202 is placed on the gate insulator film.
The state shown in FIG. 12B is obtained by forming an interlayer dielectric film (not shown) on the structure shown in FIG. 12A and forming contact electrodes 1203 and 1204 in contact with the source and drain regions on the interlayer dielectric film. Also, conductive interconnects extending from the contacted electrodes are formed. Contact holes 1205 and 1206 are formed in the interlayer dielectric film (not shown). Doped regions are connected with the contact electrodes via these contact holes.
In this structure, to allow sufficient margin for the accuracy at which the active layer 1201 is aligned, the accuracy at which the contact holes 1205 and 1206 are aligned, and the accuracy at which the electrodes 1203 and 1204 are aligned, extra area given by dimension a is necessary. In particular, sufficient margin is necessary so that the active layer 1201 and the contact hole 1206 are aligned. Also, sufficient margin is needed to permit the contact hole 1206 and the electrode 1204 to be aligned. Hence, the dimension a is necessitated.
The active matrix liquid crystal display is required to increase the aperture ratio of the pixel area as high as possible. In the abovedescribed structure, however, the electrodes used for contacts occupy a large area. This makes it impossible to enhance the transmittance.
Generally, an aperture ratio of 100% is impossible to achieve because the source line 22 and gate line 15 take up areas, as shown in FIG. 7. Accordingly, in order to increase the aperture ratio, it is necessary to minimize the area occupied by the electrode pattern that is necessary for making contacts.
For example, in the structure shown in FIG. 7, the source line 22 and electrode 23 have areas not used for contacts and result in a decrease in the aperture ratio. These areas are necessary to secure sufficient margin for alignments. After this alignment step, these areas are dead spaces and block light, thus deteriorating the aperture ratio.
Also, ordinary integrated circuits have the following problems. Some active matrix liquid crystal displays have built-in peripheral drive circuits. That is, a peripheral drive circuit for driving an active matrix circuit is integrated with the active matrix circuit on the same substrate. Of course, the peripheral drive circuit is composed of TFTs. To miniaturize the whole device, the peripheral drive circuit needs to have a higher packaging density.
With the general TFT pattern as shown in FIG. 12, however, various difficulties are encountered in enhancing the packaging density. One difficult is that the dimension a cannot be reduced to an infinitesimal value. This dimension is associated with the shrinkage of the glass substrate and mask alignment accuracy during fabrication steps and so it is difficult to reduce the dimension below a certain value. Especially, in the case of an integrated circuit using a large-area substrate made of glass that shrinks, it is important to secure the aforementioned alignment accuracy. Also, where smaller design rules are adopted, it is customary to reduce the contact holes accordingly. However, reducing the contact holes produces several problems such as increase in the contact resistance and poor contact.
For instance, if 5-micrometer design rules are replaced by 3-micrometer design rules, the contact area decreases from (5 .mu.m).sup.2 =25 .mu.m.sup.2 to (3 .mu.m).sup.2 =9 .mu.m.sup.2. That is, the contact area decreases to near one third. If the design rules are varied from 5 .mu.m rules to 3 .mu.m rules in this way, the treated current is not reduced to one third. Therefore, in this case, the current density in the contacts is approximately tripled. Under this condition, local heating tends to destroy the contacts and produce defects.
We have experimentally confirmed that, where smaller design rules are used, the contacts are destroyed at many locations, resulting in defects. Since it is necessary to provide smaller circuit areas, there will be an increasing need for smaller design rules. As the design rules diminish as described above, the contact area decreases in proportion to the squares of the design rules. This circumstance will pose more serious problems.